AD9779_15 Datasheet, PDF (6/56 Pages) Analog Devices – Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters

AD9776/AD9778/AD9779
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter
Conditions
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
Maximum Input Data Rate at Interpolation
1×
2×
4×
8×
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)¹
Output VOUT Logic High
Output VOUT Logic Low
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)
SYNC_I+ = VIA, SYNC_I− = VIB
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN2
LVDS Input Rate
Set-Up Time, SYNC_I to DAC Clock
Hold Time, SYNC_I to DAC Clock
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, RO
Single-ended
Maximum Clock Rate
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage (CLK+, CLK−)³
Common-Mode Voltage
Maximum Clock Rate⁴
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Min Typ Max Unit
2.0
V
0.8 V
300
MSPS
250
MSPS
200
MSPS
125
MSPS
2.4
V
0.4 V
825
−100
20
80
−0.2
1
1575
+100
120
125
mV
mV
mV
Ω
MSPS
ns
ns
825
1575 mV
1025
mV
150 200 250 mV
1150
1250 mV
80 100 120 Ω
1
GHz
400 800 2000 mV
300 400 500 mV
1
GSPS
40
MHz
12.5 ns
12.5 ns
1 _{Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests}
using an external buffer for this signal.
2 _{Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C.}
3 _{When using the PLL, a differential swing of 2 V p-p is recommended.}
4 _{Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.}
Rev. A | Page 6 of 56