AD9518-0 Datasheet, PDF (6/64 Pages) Analog Devices – 6-Output Clock Generator

AD9518-0
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Input Sensitivity, Differential
Min
Typ
Max
Unit
0¹
2.4
GHz
0¹
1.6
GHz
150
mV p-p
Input Level, Differential
2
V p-p
Input Common-Mode Voltage, VCM 1.3
Input Common-Mode Range, VCMR
1.3
Input Sensitivity, Single-Ended
Input Resistance
3.9
Input Capacitance
1.57
1.8
1.8
150
4.7
5.7
2
V
V
mV p-p
kΩ
pF
1 _{Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.}
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
Max
Unit
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
2950
MHz
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
VS_LVPECL −
1.12
VS_LVPECL −
2.03
550
VS_LVPECL − VS_LVPECL −
V
0.98
0.84
VS_LVPECL − VS_LVPECL −
V
1.77
1.49
790
980
mV
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 16 for peak-to-peak
differential amplitude
This is VOH − VOL for each leg of a differential pair for
default amplitude setting with driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver toggling
is roughly 2× these values (see Figure 16 for variation
over frequency)
TIMING CHARACTERISTICS
Table 5.
Parameter
Min
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL,
CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution 835
Configuration
Clock Distribution Configuration
773
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS¹
LVPECL Outputs That Share the
Same Divider
LVPECL Outputs on Different
Dividers
All LVPECL Outputs Across Multiple
Parts
Typ
Max
Unit
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
70
180
ps
20% to 80%, measured differentially
70
180
ps
80% to 20%, measured differentially
995
1180
ps
See Figure 28
933
1090
ps
See Figure 30
0.8
ps/°C
5
15
ps
13
40
ps
220
ps
1 _{This is the difference between any two similar delay paths while operating at the same voltage and temperature.}
Rev. C | Page 6 of 64