AD9461_15 Datasheet, PDF (6/28 Pages) Analog Devices – 16-Bit, 130 MSPS IF Sampling ADC

AD9461
TIMING DIAGRAMS
N–1
N
A_IN
N+1
CLK+
t_CLKL
t_CLKH
1/f_S
CLK–
t_PD
DATA OUT
DCO+
N – 13
N – 12
13 CLOCK CYCLES
N + 13
N + 14
N + 15
N
N+1
DCO–
t_CPD
Figure 2. LVDS Mode Timing Diagram
VIN
CLK–
CLK+
DX
DCO+
DCO–
N
N–1
t_CLKL
t_CLKH
t_PD
N+1
N+2
13 CLOCK CYCLES
N – 13
N – 12
N–1
N
Figure 3. CMOS Timing Diagram
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