AD9267 Datasheet, PDF (6/24 Pages) Analog Devices – 10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator

AD9267
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.
Table 4.
Parameter¹
CLOCK INPUT PARAMETERS
Input CLK Rate
CLK± Period
CLK± Duty Cycle
CLOCK INPUT PARAMETERS
Conversion Rate
CLK± Period
CLK± Duty Cycle
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)²
DCO± Propagation Delay (tDCO)
DCO± to Data Skew (tSKEW)
Aperture Uncertainty (Jitter, tJ)
WAKE-UP TIME
Power-Down Power
Standby Power
Sleep Power
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE³
SCLK Period (tSCLK)
SCLK Pulse Width High Time (tSHIGH)
SCLK Pulse Width Low Time (tSLOW)
SDIO to SCLK Set-Up Time (tSDS)
SDIO to SCLK Hold Time (tSDH)
CSB to SCLK Set-Up Time (tSS)
CSB to SCLK Hold Time (tSH)
Conditions/Comments
Using clock multiplier
Direct clocking
Temp Min
Full
30
Full
6.25
Full
40
Full
608
Full
1.48
Full
40
Full
160
Full
-60
Full
180
Full
25°C
25°C
25°C
25°C
Full
Full
16
Full
16
Full
5
Full
2
Full
5
Full
2
1 _{See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.}
2 _{Output propagation delay is measured from CLK± 50% transition to data D0±x to D3±x 50% transition, with 5 pF load.}
3 _{See Figure 42 and the Serial Port Interface (SPI) section.}
Typ
50
640
1.5625
50
510
268
200
1
3
9
15
100
Timing Diagram
CLK±
DCO±
D0±x TO D3±x
t_DCO
t_PD
t_SKEW
Figure 2. Timing Diagram
Max Unit
160 MSPS
33.3 ns
60
%
672 MSPS
1.72 ns
60
%
840 ps
570 ps
280 Ps
ps rms
Μs
μs
μs
ns
40
ns
ns
ns
ns
ns
ns
ns
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