AD9248 Datasheet, PDF (6/23 Pages) Analog Devices – 14-Bit, 20/40/65 MSPS Dual A/ D Converter

AD9248
Preliminary Technical Data
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications
Parameter
SWITCHING PERFORMANCE
Max Conversion Rate
Min Conversion Rate
CLK Period
CLK Pulsewidth High¹
CLK Pulsewidth Low¹
DATA OUTPUT PARAMETER
Output Delay² (t_PD)
Pipeline Delay (Latency)
Aperture Delay (t_A)
Aperture Uncertainty (t_J)
Wake-Up Time³
OUT-OF-RANGE RECOVERY
TIME
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
VI
V
V
V
V
VI
V
V
V
V
V
AD9248BST/BCP-
20
Min Typ Max
20
1
50.0
15.0
15.0
2
3.5 6
7
1.0
0.5
2.5
2
AD9248BST/BCP-
40
Min Typ Max
40
1
25.0
8.8
8.8
2
3.5 6
7
1.0
0.5
2.5
2
AD9248BST/BCP-
65
Min Typ Max
65
1
15.4
6.2
6.2
2
3.5 6
7
1.0
0.5
2.5
2
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
Ps rms
ms
1 _{The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20).}
2 _{Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.}
3 _{Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.}
Specifications subject to change without notice.
Rev. PrE | Page 6 of 23