AD7952 Datasheet, PDF (6/32 Pages) Analog Devices – 14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC

AD7952
Parameter
Symbol Min
Typ
Max
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES²
(See Figure 43, Figure 44, and Figure 46)
External SDCLK, SCCLK Setup Time
t31
5
External SDCLK Active Edge to SDOUT Delay
t32
2
18
SDIN/SCIN Setup Time
t33
5
SDIN/SCIN Hold Time
t34
5
External SDCLK/SCCLK Period
t35
25
External SDCLK/SCCLK High
t36
10
External SDCLK/SCCLK Low
t37
10
1 _{In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.}
2 _{In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.}
3 _{In serial master read during convert mode. See Table 4 for serial master read after convert mode.}
Unit
ns
ns
ns
ns
ns
ns
ns
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SDCLK First Edge Delay Minimum
t18
3
20
20
20
ns
Internal SDCLK Period Minimum
t19
30
60
120
240
ns
Internal SDCLK Period Maximum
t19
45
90
180
360
ns
Internal SDCLK High Minimum
t20
12
30
60
120
ns
Internal SDCLK Low Minimum
t21
10
25
55
115
ns
SDOUT Valid Setup Time Minimum
t22
4
20
20
20
ns
SDOUT Valid Hold Time Minimum
t23
5
8
35
90
ns
SDCLK Last Edge to SYNC Delay Minimum
t24
5
7
35
90
ns
BUSY High Width Maximum
t28
Warp Mode
1.60
2.35
3.75
6.75
μs
Normal Mode
1.85
2.60
4.00
7.00
μs
Impulse Mode
2.10
2.85
4.25
7.25
μs
1.6mA
I_OL
TO OUTPUT
PIN _CL
60pF
1.4V
500µA
I_OH
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C_L OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF
0.8V
t_DELAY
2V
0.8V
2V
t_DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
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