AD7785 Datasheet, PDF (6/32 Pages) Analog Devices – 3-Channel, Low Noise, Low Power, 20-Bit ∑-Δ ADC with On-Chip In-Amp and Reference

AD7785
TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter^{1, 2}
t3
t4
Read Operation
t1
t2 ³
t55, ⁶
t6
t7
Write Operation
t8
t9
t10
t11
Limit at TMIN, TMAX (B Version)
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
SCLK active edge to data valid delay⁴
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
CS falling edge to SCLK active edge setup time⁴
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
1 _{Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.}
2 _{See Figure 3 and Figure 4.}
3 _{These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.}
4 _{SCLK active edge is the falling edge of SCLK.}
5 _{These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number}
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 _{RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,}
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
I_SINK (1.6mA WITH DV_DD = 5V,
100µA WITH DV_DD = 3V)
TO
OUTPUT
PIN
50pF
1.6V
I_SOURCE (200µA WITH DV_DD = 5V,
100µA WITH DV_DD = 3V)
Figure 2. Load Circuit for Timing Characterization
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