AD7715_15 Datasheet, PDF (6/40 Pages) Analog Devices – 16-Bit, Sigma-Delta ADC

AD7715
Parameter ¹
Min
Typ
Max
Unit
Conditions/Comments
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
VOH, Output High Voltage
DVDD − 0.6
0.4
V
V
ISINK = 100 μA except for MCLK OUT¹²
ISOURCE = 100 μA except for MCLK OUT¹²
Floating State Leakage Current
±10
μA
Floating State Output Capacitance¹³
9
pF
Data Output Coding
Binary
Unipolar mode
Offset binary
Bipolar mode
1 _{Temperature range as follows: A version, −40°C to +85°C.}
2 _{A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the}
temperature of interest.
3 _{Recalibration at any temperature removes these drift errors.}
4 _{Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.}
5 _{Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.}
6 _{Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for}
bipolar ranges.
7 _{Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.}
8 _{These numbers are guaranteed by design and/or characterization.}
9 _{This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AVDD + 30 mV or go more negative}
than AGND − 30 mV.
10 _{The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive}
than AVDD + 30 mV or go more negative than AGND − 30 mV.
11 _{VREF = REF IN(+) − REF IN(−).}
12 _{These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.}
13 _{Sample tested at 25°C to ensure compliance.}
Rev. D | Page 6 of 40