AD7685BRM Datasheet, PDF (6/28 Pages) Analog Devices – 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN

AD7685
−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 5. VDD = 2.3V to 4.5 V¹
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ Max Unit
0.7
3.2 μs
1.8
μs
5
μs
10
ns
25
ns
29
ns
35
ns
40
ns
12
ns
12
ns
5
ns
24
ns
30
ns
35
ns
18
ns
22
ns
25
ns
30
ns
0
ns
5
ns
8
ns
5
ns
4
ns
36
ns
1 _{See Figure 3 and Figure 4 for load conditions.}
500µA I_OL
TO SDO
C_L
50pF
1.4V
500µA I_OH
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
t_DELAY
70% VIO
2V OR VIO – 0.5V¹
0.8V OR 0.5V²
t_DELAY
2V OR VIO – 0.5V¹
0.8V OR 0.5V²
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. B | Page 6 of 28