AD7663_15 Datasheet, PDF (6/24 Pages) Analog Devices – 16-Bit, 250 kSPS CMOS ADC

AD7663
Pin
No.
1
2
3, 6, 7,
44–48
4
5
8
9, 10
11, 12
13
14
15
16
17
18
19
20
PIN FUNCTION DESCRIPTION
Mnemonic
AGND
AVDD
NC
Type Description
P Analog Power Ground Pin.
P Input Analog Power Pin. Nominally 5 V.
No Connect.
BYTESWAP DI
OB/2C
DI
SER/PAR
DI
D[0:1]
DO
D[2:3] or
DI/O
DIVSCLK[0:1]
D[4]
DI/O
or EXT/INT
D[5]
DI/O
or INVSYNC
D[6]
DI/O
or INVSCLK
D[7]
DI/O
or RDC/SDIN
OGND
P
OVDD
P
DVDD
P
DGND
P
Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output
on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal
shift register.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the Data bus are used as a Serial Port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs
are in high impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial
Master Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down,
if desired, the internal serial clock that clocks the data output. In the other serial modes, these
pins are high impedance outputs.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for
choosing the internal or an external data clock, called respectively, Master and Slave Modes.
With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT
set to a logic HIGH, output data is synchronized to an external clock signal connected to the
SCLK input, and external clock is gated by CS.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both master and slave mode.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground.
–6–
REV. B