AD7658-1_15 Datasheet, PDF (6/32 Pages) Analog Devices – 250 kSPS, 6-Channel, Simultaneous

AD7656-1/AD7657-1/AD7658-1
Parameter
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating-State Leakage Current
Floating-State Output Capacitance²
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time^{1, 2}
Throughput Rate
POWER REQUIREMENTS
VDD
VSS
AVCC
DVCC
VDRIVE
ITOTAL3
Normal Mode—Static
Min
Typ
VDRIVE − 0.2
Twos
complement
−5
−5
4.75
4.75
2.7
Max
0.2
±10
10
3.1
550
250
+16.5
−16.5
5.25
5.25
5.25
18
Normal Mode—Operational
26
ISS (Operational)
0.25
IDD (Operational)
0.25
Partial Power-Down Mode
7
Full Power-Down Mode (STBY Pin)
60
Power Dissipation
Normal Mode—Static
94
Normal Mode—Operational
140
Partial Power-Down Mode
40
Full Power-Down Mode
315
(STBY Pin)
1 _{See the Terminology section.}
2 _{Sample tested during initial release to ensure compliance.}
3 _{Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC.}
Unit
V
V
µA
pF
µs
ns
kSPS
V
V
V
V
V
mA
mA
mA
mA
mA
µA
mW
mW
mW
µW
Data Sheet
Test Conditions/Comments
ISOURCE = 200 µA
ISINK = 200 µA
Parallel interface mode only
For the 4 × VREF range, VDD = 10 V to 16.5 V
For the 4 × VREF range, VSS= −10 V to −16.5 V
Digital inputs = 0 V or VDRIVE
AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = +5.25 V, VDD =
+16.5 V, VSS = −16.5 V
VSS = −16.5 V, fSAMPLE = 250 kSPS
VDD = 16.5 V, fSAMPLE = 250 kSPS
AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V,
VSS = −16.5 V
SCLK on or off, AVCC = DVCC = VDRIVE = +5.25 V,
VDD = +16.5 V, VSS = −16.5 V
AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS
Rev. D | Page 6 of 32