AD7305BRUZ Datasheet, PDF (6/20 Pages) Analog Devices – 3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC

AD7304/AD7305
SDI
SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
CS
t_CSS
LDAC
t_LD1
t_CSH
t_LD2
SDI
CLK
LDAC
CLR
FS
V_OUT
ZS
t_DS
t_CL
t_DH
t_CH
t_LDW
t_S
Figure 4. AD7304 General Timing Diagram
t_CLRW
±1 LSB
ERROR BAND
t_S
SDI/SHDN
I_DD
t_SDN
t_SDR
Figure 5. AD7304 Timing Diagram Zoom In
Table 4. AD7304 Control Logic Truth Table
CS ¹ CLK¹ LDAC CLR¹ Serial Shift Register Function
HX
H
H
No effect
L ↑+ H
H
Data advanced 1 bit
↑+ L
H
HX
L
H
No effect
H
No effect
HX
H
HX
H
↓– No effect
↑+ No effect
Input REG Function
No effect
No effect
Updated with SR contents²
Latched with SR contents²
Loaded with 0x00
Latched with 0x00
DAC Register Function
No effect
No effect
No effect
All input register contents transferred³
Loaded with 0x00
Latched with 0x00
1 _{↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.}
2 _{One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1).}
3 _{LDAC is a level-sensitive input.}
Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format
MSB
LSB
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
AD7304 SAC
SDC
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become
high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed
in shutdown mode.
Rev. C | Page 6 of 20