AD1981BBSTZ Datasheet, PDF (6/32 Pages) Analog Devices – AC 97 SoundMAX Codec

AD1981B
Parameter
BIT_CLK Low Pulse Width
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
OBIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
BSDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to High Z Delay
Propagation Delay
S RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
Symbol
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
Min
Typ
32.56 38
48.0
20.8
5
2.5
5
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
0
15
1 _{Guaranteed but not tested.}
2 _{Output jitter is directly dependent on crystal input jitter.}
O ^{3 Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.}
Max Unit
ns
kHz
ms
ns
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
1.0
ms
ns
25
ns
15
ns
50
ns
15
ns
L _RESET
BIT_CLK
E _{SDATA_IN}
t_{RST_LOW}
t_RST2CLK
t_TRI2ACTV
t_TRI2ACTV
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
T _SYNC
E ^BIT_CLK
t_{SYNC_HIGH}
t_SYNC2CLK
Figure 3. Warm Reset Timing
Rev. C | Page 6 of 32