AD9518-4 Datasheet, PDF (58/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 1.6 GHz VCO

AD9518-4
Data Sheet
Reg.
Addr
(Hex) Bits
0x1E1 4
3
2
1
0
Name
Power down clock input section
Power down VCO clock interface
Power down VCO and CLK
Select VCO or CLK
Bypass VCO divider
Description
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 48. System
Reg.
Addr.
(Hex) Bits
Name
0x230 2
Power down SYNC
1
Power down distribution
reference
0
Soft sync
Description
Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down sync circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft sync bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a sync.
0: same as SYNC high (default).
1: same as SYNC low.
Table 49. Update All Registers
Reg.
Addr
(Hex) Bits
Name
0x232 0
Update all registers
Description
This bit must be set to 1b to transfer the contents of the buffer registers into the active
registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is,
it does not have to be set back to 0b.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
Rev. B | Page 58 of 64