ADE7758 Datasheet, PDF (57/68 Pages) Analog Devices – Poly Phase Multifunction Energy Metering IC with Per Phase Information

ADE7758
ADE7758 SERIAL READ OPERATION
During a data read operation from the ADE7758, data is shifted
out at the DOUT logic output on the rising edge of SCLK. As
was the case with the data write operation, a data read must be
preceded with a write to the communications register.
With the ADE7758 in communications mode and CS logic low,
an 8-bit write to the communications register first takes place.
The MSB of this byte transfer must be a 0, indicating that the
next data transfer operation is a read. The seven LSBs of this
byte contain the address of the register that is to be read. The
ADE7758 starts shifting out of the register data on the next
rising edge of SCLK (see Figure 93). At this point, the DOUT
logic output switches from a high impedance state and starts
driving the data bus. All remaining bits of register data are
shifted out on subsequent SCLK rising edges. The serial
interface enters communications mode again as soon as the
CS
t₁
t₉
SCLK
read has been completed. The DOUT logic output enters a high
impedance state on the falling edge of the last SCLK pulse. The
read operation may be aborted by bringing the CS logic input
high before the data transfer is completed. The DOUT output
enters a high impedance state on the rising edge of CS.
When an ADE7758 register is addressed for a read operation,
the entire contents of that register are transferred to the serial
port. This allows the ADE7758 to modify its on-chip registers
without the risk of corrupting data during a multibyte transfer.
Note that when a read operation follows a write operation, the
read command (i.e., write to communications register) should
not happen for at least 1.1 µs after the end of the write operation.
If the read command is sent within 1.1 µs of the write operation,
the last byte of the write operation may be lost.
t₁₃
t₁₀
DIN
DOUT
0 A6 A5 A4 A3 A2 _{A1 A0}
t₁₁
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 93. Serial Interface Read Timing Diagram
DB7
t₁₂
DB0
LEAST SIGNIFICANT BYTE
Rev. A | Page 57 of 68