ADUC814BRUZ Datasheet, PDF (56/72 Pages) Analog Devices – MicroConverter®, Small Package 12-Bit ADC with Embedded Flash MCU

ADuC814
Timer 2 Generated Baud Rates
Baud rates can also be generated using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16
times before a bit is transmitted/received. Because Timer 2 has a
16-bit autoreload mode, a wide range of baud rates is possible
using Timer 2.
Modes 1 and 3 Baud Rate = (1/16) × (Timer 2 Overflow Rate)
Therefore, when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles and not every core
machine cycle as before. Therefore, it increments six times faster
than Timer 1, and therefore baud rates six times faster are
possible. Because Timer 2 has 16-bit autoreload capability, very
low baud rates are still possible. Timer 2 is selected as the baud
rate generator by setting the CLK and/or RCLK in T2CON. The
baud rates for transmit and receive can be simultaneously
different. Setting RCLK and/or TCLK puts Timer 2 into its baud
rate generator mode as shown in Figure 53.
In this case, the baud rate is given by the formula
Modes 1 and 3 Baud Rate = (Core Clk)/
(32 × [65536 – (RCAP2H, RCAP2L)])
Table 28 shows some commonly used baud rates and how they
could be calculated from a core clock frequency of 2.0971 MHz
and 16.7772 MHz.
Table 28. Commonly Used Baud Rates, Timer 2
Ideal
Baud
Core RCAP2H RCAP2L
CLK Value Value
Actual
Baud
19200 16.78 –1 (FFH) –27 (E5H) 19418
9600 16.78 –1 (FFH) –55 (C9H) 9532
2400 16.78 –1 (FFH) –218 (26H) 2405
1200 16.78 –2 (FEH) –181 (4BH) 1199
9600 2.10 –1 (FFH) –7 (FBH)
9362
2400 2.10 –1 (FFH) –27 (ECH) 2427
1200 2.10 –1 (FFH) –55 (D7H) 1191
%
Error
1.14
0.7
0.21
0.02
2.4
1.14
0.7
TIMER 1
OVERFLOW
NOTE: OSCILLATOR FREQUENCY IS DIVIDED BY 2, NOT 12
CORE
CLK*
÷2
CONTROL
C/T2 = 0
T2
C/T2 = 1
PIN
TR2
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
TL2
(8 BITS)
RCAP2L
TL2
(8 BITS)
TIMER 2
OVERFLOW
RELOAD
RCAP2H
÷2
0
1
0
1
0
1
SMOD
RCLK
÷16
TCLK
÷16
RX
CLOCK
TX
CLOCK
T2EX
PIN
EXF 2
TIMER 2
INTERRUPT
TRANSITION
DETECTOR
CONTROL
EXEN2
*THE CORE CLOCK IS THE OUTPUT OF THE PLL
Figure 53. Timer 2, UART Baud Rates
Rev. A | Page 56 of 72