ADSP-21489BSWZ-4B Datasheet, PDF (54/68 Pages) Analog Devices – SHARC Processor

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
JTAG Test Access Port and Emulation
Table 54. JTAG Test Access Port and Emulation
Parameter
Min
Max
Timing Requirements
t_TCK
TCK Period
20
t_STAP
TDI, TMS Setup Before TCK High
5
t_HTAP
TDI, TMS Hold After TCK High
6
t_SSYS¹
System Inputs Setup Before TCK High
7
t_HSYS¹
System Inputs Hold After TCK High
18
t_TRSTW
TRST Pulse Width
4t_CK
Switching Characteristics
t_DTDO
t_DSYS²
TDO Delay from TCK Low
System Outputs Delay After TCK Low
10
t_TCK ÷ 2 + 7
1 _{System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG2–0, DAI_Px, DPI_Px, and FLAG3–0.}
2 _{System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK and EMU.}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_STAP
t_DTDO
t_SSYS
t_DSYS
t_HTAP
t_HSYS
Figure 40. IEEE 1149.1 JTAG Test Access Port
Rev. B | Page 54 of 68 | March 2013