AD9547 Datasheet, PDF (54/104 Pages) Analog Devices – Dual/Quad Input Network Clock Generator/Synchronizer

AD9547
I²C SERIAL PORT OPERATION
The I²C interface has the advantage of requiring only two
control pins and is a de facto standard throughout the I²C
industry. However, its disadvantage is programming speed,
which is 400 kbps maximum. The AD9547 I2C port design is
based on the I2C fast mode standard from Philips, so it supports
both the 100 kHz standard mode and the 400 kHz fast mode.
Fast mode imposes a glitch tolerance requirement on the control
signals; that is, the input receivers ignore pulses of less than
50 ns duration.
The AD9547 I2C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I2C bus system, the AD9547 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9547.
The AD9547 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9547 allows for up to seven unique slave devices to occupy
the I²C bus. These are accessed via a 7-bit slave address that is
transmitted as part of an I²C packet. Only the device with a match-
ing slave address responds to subsequent I²C commands. The
device slave address is 1001xxx (the last three bits are determined
by the M0 to M2 pins). The four MSBs (1001) are hardwired,
whereas the three LSBs (xxx, determined by the M0 to M2 pins)
are programmable via the power-up state of the multifunction
pins (see the Initial M0 to M7 Pin Programming section).
I²C Bus Characteristics
A summary of the various I²C protocols appears in Table 34.
Table 34. I²C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
No acknowledge
W
Write
R
Read
The transfer of data appears graphically in Figure 57. One clock
pulse is generated for each data bit transferred. The data on the
SDA line must be stable during the high period of the clock.
The high or low state of the data line can change only when the
clock signal on the SCL line is low.
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 57. Valid Bit Transfer
Start/stop functionality appears graphically in Figure 58. The
start condition is characterized by a high-to-low transition on
the SDA line while SCL is high. The start condition is always
generated by the master to initialize data transfer. The stop
condition is characterized by a low-to-high transition on the
SDA line while SCL is high. The stop condition is always
generated by the master to terminate data transfer.
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 58. Start and Stop Condition
Every byte on the SDA line must be eight bits long. Each byte
must be followed by an acknowledge bit. Bytes are sent MSB first.
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
The no acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
SDA
SCL
S
MSB
1
2
3 TO 7
ACK FROM
SLAVE RECEIVER
8
9
1
2
Figure 59. Acknowledge Bit
3 TO 7
ACK FROM
SLAVE RECEIVER
8
9
10
P
Rev. 0 | Page 54 of 104