AD6652_15 Datasheet, PDF (53/76 Pages) Analog Devices – 12-Bit, 65 MSPS IF to Baseband Diversity Receiver

AD6652
LINK PORT
The AD6652 has two configurable link ports that provide a
seamless data interface with the TigerSHARC TS-101 series
DSP. Each link port allows the AD6652 to write output data to
the receive DMA channel in the TigerSHARC for transfer to
memory. Because they operate independently of each other,
each link port can be connected to a different TigerSHARC or
different link ports on the same TigerSHARC. Figure 59 shows
how to connect one of the two AD6652 link ports to one of the
four TigerSHARC link ports. Link Port A is configured through
Register 0x1B and Link Port B is configured through
Register 0x1D.
AD6652
LCLKIN
LCLKOUT
8
LDAT
PCLK
TigerSHARC
LCLKIN
LCLKOUT
LDAT
PCLK
Figure 59. Link Port Connection between AD6652 and TigerSHARC
LINK PORT DATA FORMAT
Each link port can output data to the TigerSHARC in five
different formats: 2-channel, 4-channel, dedicated AGC,
redundant AGC with receive signal strength indicator (RSSI)
word, and redundant AGC without RSSI word. Each format
outputs two bytes of I data and two bytes of Q data to form a
4-byte IQ pair. Because the TigerSHARC link port transfers data
in quad-word (16-byte) blocks, four IQ pairs can make up one
quad-word. If the channel data is selected (Bit 0 = 0 of 0x1B/
0x1D), then 4-byte IQ words of the four channels can be output
in succession, or alternating channel pair IQ words can be
output. Figure 60 and Figure 61 show the quad-word trans-
mitted for each case with corresponding register values for
configuring each link port.
LINK PORT
A OR B
LINK PORT A
CH 0 I, Q
(4 BYTES)
CH 1 I, Q
(4 BYTES)
CH 2 I, Q
(4 BYTES)
CH 3 I, Q
(4 BYTES)
ADDR 0x1B OR 0x1D BIT 0 = 0, BIT 1 = 0
CH 0 I, Q
(4 BYTES)
CH 1 I, Q
(4 BYTES)
CH 0 I, Q
(4 BYTES)
CH 1 I, Q
(4 BYTES)
LINK PORT B
CH 2 I, Q
(4 BYTES)
CH 3 I, Q
(4 BYTES)
CH 2 I, Q
(4 BYTES)
CH 3 I, Q
(4 BYTES)
ADDR 0x1B AND 0x1D BIT 0 = 0, BIT 1 = 1
Figure 60. Link Port Data from RCF
If AGC output is selected (Bit 0 = 1), then RSSI information can
be sent with the IQ pair from each AGC. Each link port can be
configured to output data from one AGC, or both link ports can
output data from the same AGC. If both link ports are transmit-
ting the same data, then RSSI information must be sent with the
IQ words (Bit 2 = 0). Note that the actual RSSI word is only
two bytes (12 bits appended with 4 0s), so the link port sends
two bytes of 0s immediately after each RSSI word to make a full
16-byte quad-word.
Note that Bit 0 = 1, Bit 1 = 0, and Bit 2 = 1 is not a valid
configuration. Bit 2 must be set to 0, to output AGC A IQ and
RSSI words on Link Port A and AGC B IQ and RSSI words on
Link Port B.
LINK PORT
A OR B
LINK PORT
A OR B
LINK PORT A
AGC A I, Q
(4 BYTES)
AGC B I, Q
(4 BYTES)
AGC A I, Q
(4 BYTES)
AGC B I, Q
(4 BYTES)
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0
AGC A I, Q
(4 BYTES)
AGC A RSSI
(4 BYTES)
AGC B I, Q
(4 BYTES)
AGC B RSSI
(4 BYTES)
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1
AGC A I, Q
(4 BYTES)
AGC A RSSI
(4 BYTES)
AGC A I, Q
(4 BYTES)
AGC A RSSI
(4 BYTES)
LINK PORT B
AGC B I, Q
(4 BYTES)
AGC B RSSI
(4 BYTES)
AGC B I, Q
(4 BYTES)
AGC B RSSI
(4 BYTES)
ADDR 0x1B AND 0x1D BIT 0 = 1, BIT 1 = 1, BIT 2 = 0
Figure 61. Link Port Data from AGC
LINK PORT TIMING
Both link ports run off of PCLK, which can be externally
provided to the chip (Address 0x1E Bit 0 = 0) or generated from
the master clock of the AD6652 (Address 0x1E Bit 0 = 1). This
register boots to 0 (slave mode) and allows the user to control
the data rate coming from the AD6652. PCLK can be run as fast
as 100 MHz in slave mode.
The link port provides 1-byte data words (LA[7:0], LB[7:0]
pins) and output clocks (LACLKOUT, LBCLKOUT pins) in
response to a ready signal (LACLKIN, LBCLKIN pins) from the
receiver. Each link port transmits 8 bits on each edge of
LCLKOUT, requiring 8 LCLKOUT cycles to complete
transmission of the full 16 bytes of a TigerSHARC quad-word.
Due to the TigerSHARC link port protocol, the AD6652 must
wait at least 6 PCLK cycles after the TigerSHARC is ready to
receive data, as indicated by the TigerSHARC setting the
respective AD6652 LCLKIN pin high. Once the AD6652 link
port has waited the appropriate number of PCLK cycles and has
begun transmitting data, the TigerSHARC does a connectivity
check by sending the AD6652 LCLKIN low and then high while
the data is being transmitted. This tells the AD6652 link port
that the TigerSHARC’s DMA is ready to receive the next quad-
word after completion of the current quad-word. Because the
connectivity check is done in parallel to the data transmission,
the AD6652 can stream uninterrupted data to the TigerSHARC.
LCLKIN
TigerSHARC READY TO
RECEIVE QUAD-WORD
TigerSHARC READY TO
RECEIVE NEXT QUAD-WORD
LCLKOUT
LDAT[7:0]
WAIT ≥ 6 CYCLES
D0 D1 D2 D3 D4
D15 D0 D1 D2
NEXT QUAD-WORD
Figure 62. Link Port Data Transfer
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