ADV7310_15 Datasheet, PDF (51/84 Pages) Analog Devices – Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs

Adaptive Filter Control Application
Figures 45 and 46 show typical signals to be processed by the
adaptive filter control block.
⌬: 692mV
@: 446mV
⌬: 332ns
@: 12.8ms
ADV7310/ADV7311
When changing the adaptive filter mode to Mode B [Address 15h,
Bit 6], the following output can be obtained:
⌬: 674mV
@: 446mV
⌬: 332ns
@: 12.8ms
Figure 45. Input Signal to Adaptive Filter Control
⌬: 692mV
@: 446mV
⌬: 332ns
@: 12.8ms
Figure 46. Output Signal after Adaptive Filter Control
The following register settings were used to obtain the results
shown in Figure 46, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
Table XIV.
Address
Register Setting
00h
FCh
01h
38h
02h
20h
10h
00h
11h
81h
15h
80h
20h
00h
38h
ACh
39h
9Ah
3Ah
88h
3Bh
28h
3Ch
3Fh
3Dh
64h
All other registers are set as normal/default.
Figure 47. Output Signal from Adaptive Filter Control
The adaptive filter control can also be demonstrated using the
internally generated cross hatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].
Table XV.
Address
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
Register Setting
FCh
38h
20h
00h
85h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
REV. A
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