ADSP-2115_15 Datasheet, PDF (50/64 Pages) Analog Devices – ADSP-2100 Family DSP Microcomputers

ADSP-21xx
TIMING PARAMETERS (ADSP-2103/2162/2164)
SERIAL PORTS
Parameter
Timing Requirement:
t_SCK SCLK Period
t_SCS DR/TFS/RFS Setup before SCLK Low
t_SCH DR/TFS/RFS Hold after SCLK Low
t_SCP SCLK_in Width
Switching Characteristic:
t_CC
t_SCDE
t_SCDV
t_RH
t_RD
t_SCDH
t_TDE
t_TDV
t_SCDD
t_RDV
CLKOUT High to SCLK_out
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFS_out Hold after SCLK High
TFS/RFS_out Delay from SCLK High
DT Hold after SCLK High
TFS (alt) to DT Enable
TFS (alt) to DT Valid
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero)
to DT Valid
10.24 MHz
Min Max
97.6
8
10
28
24.4 39.4
0
28
0
28
0
0
18
30
20
Frequency
Dependency
Min
Max
t_CK
0.25t_CK
0.25t_CK + 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
SCLK
DR
RFS_IN
TFS_IN
RFS_OUT
TFS_OUT
DT
TFS
( ALTERNATE
FRAME MODE )
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
t_CC
t_RD
t_RH
t_SCDV
t_SCDE
t_TDE
t_TDV
t_CC
t_SCS t_SCH
t_SCP
t_SCK
t_SCP
t_SCDH
t_SCDD
t_RDV
Figure 44. Serial Ports
–50–
REV. B