EVAL-AD7470_07 Datasheet, PDF (5/20 Pages) Analog Devices – Evaluation Board for 10-/12-Bit High Speed, Low Power ADCs

EVAL-CONTROL BRD2 INTERFACING
Interface to the EVAL-CONTROL BRD2 via a 96-way
connector, J1. The pinout for the J1 connector is shown in
Figure 2 and its pin designations are given in Table 4.
1
32
A
B
C
1
32
Figure 2. Pin Configuration for the 96-Way Connector, J1
Table 3. 96-Way Connector Pin Description
Signal Description
D0 to Data Bit 0 to Data Bit 11. Three-state TTL outputs. D11
D11 is the MSB.
SCLK0
Serial Clock Zero. This continuous clock can be
connected to the CLKIN pin of the AD7470/AD7472
via LK3.
+5VD
Digital +5 V supply. This can be used to provide a
separate +5 V supply for the digital logic if required
via LK2.
RD
Read. This is an active low logic input connected to the
RD pin of the AD7470/AD7472 via LK5.
CS
Chip Select. This is an active low logic input connected
to the CS pin of the AD7470/AD7472 via LK6.
FL0
Flag Zero. This logic input is connected to the CONVST
input of the AD7470/AD7472 via LK4.
IRQ2 Interrupt Request 2. This is a logic output and is
connected to the BUSY logic output on the
AD7470/AD7472.
DGND
Digital Ground. These lines are connected to the
digital ground plane on the evaluation board. It
allows the user to provide the digital supply via
the connector along with the other digital signals.
AGND Analog Ground. These lines are connected to the
analog ground plane on the evaluation board.
AVSS
Negative Supply Voltage. This provides a negative
supply to the on-board op amps via LK9.
AVDD
Positive Supply Voltage. This provides a positive
supply to the op amps, the reference, the
AD7470/AD7472, and the digital logic.
EVAL-AD7470/AD7472
Table 4. 96-Way Connector Pin Functions¹
Pin
Row A
Row B
1
2
D0
3
D1
4
DGND
DGND
5
D2
6
D3
7
SCLK0
D4
8
+5VD
+5VD
9
RD
D5
10
D6
11
D7
12
DGND
DGND
13
D8
14
D9
15
D10
16
DGND
DGND
17
FL0
D11
18
19
20
DGND
DGND
21
AGND
AGND
22
AGND
AGND
23
AGND
AGND
24
AGND
AGND
25
AGND
AGND
26
AGND
AGND
27
AGND
28
AGND
29
AGND
AGND
30
AGND
31
AVSS
AVSS
32
AVDD
AVDD
Row C
DGND
SCLK0
+5VD
CS
DGND
DGND
IRQ2
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVSS
AVDD
1_{The unused pins of the 96-way connector are not shown.}
While the AD7470/AD7472 data sheet specifies a maximum
clock frequency of 30 MHz and 26 MHz for the parts, the
DSP and the on-board crystal oscillator output a 20 MHz and
25 MHz clock, respectively. Therefore, the maximum sampling
frequency is less than specified on the data sheet. An external
clock frequency (up to the maximum specified on the data
sheet) can be applied via the external socket, SK1.
Rev. C | Page 5 of 20