ADUM4150 Datasheet, PDF (5/21 Pages) Analog Devices – 5 kV, 6-Channel, SPIsolator Digital

Data Sheet
ADuM4150
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching¹
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time²
Jitter, High Speed
DCLK³
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx4 Minimum Input Skew⁵
A Grade
B Grade
Symbol Min Typ Max Min Typ Max Unit Test Conditions/Comments
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
12.5
1
8.3
40
30
12.5
3
3
1
12.5 MHz
40 Mbps Within PWD limit
20 ns
50% input to 50% output
ns
Within PWD limit
3
ns
|tPLH − tPHL|
3
ns
ns
DRFAST
tPHL, tPLH
PW
12.5
PWD
MSSSETUP 1.5
JHS
1
40
30
12.5
3
10
1
40 Mbps Within PWD limit
30 ns
50% input to 50% output
ns
Within PWD limit
3
ns
|tPLH − tPHL|
ns
ns
40
40 MHz
tPHL, tPLH
60
40 ns
tPMCLK + tPSO + 3 ns
PWD
3
3
ns
|tPLH − tPHL|
PW
12
12
ns
Within PWD limit
DCLKERR −4 +2.4 +9 −3 +2.5 +8 ns
tPDCLK − (tPMCLK + tPSO)
JDCLK
1
1
ns
DRSLOW
tPHL, tPLH 0.1
PW
4
JLS
tVIx SKEW
10
250
2.6 0.1
4
2.5
10
250 kbps Within PWD limit
2.6 µs
50% input to 50% output
µs
Within PWD limit
2.5 µs
ns
1 _{Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.}
2 _{The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output}
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 _{tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference}
between the DCLK signal and the round trip propagation delay.
4 _{VIx = VIA or VIB.}
5 _{An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the}
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 5 of 21