ADUM1210 Datasheet, PDF (5/20 Pages) Analog Devices – Dual-Channel Digital Isolator

ADuM1210
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, per Channel,
Quiescent
Output Supply Current, per Channel,
Quiescent
Total Supply Current, Two Channels¹
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps
VDD1 Supply Current
VDD2 Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
Minimum Pulse Width²
Maximum Data Rate³
Propagation Delay⁴
Pulse Width Distortion, |tPLH − tPHL|⁴
Change vs. Temperature
Propagation Delay Skew⁵
Channel-to-Channel Matching,
Codirectional Channels⁶
Channel-to-Channel Matching,
Opposing-Directional Channels⁶
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output⁷
Common-Mode Transient Immunity
at Logic Low Output⁷
Refresh Rate
Input Dynamic Supply Current,
per Channel⁸
Output Dynamic Supply Current,
per Channel⁸
Symbol Min
IDDI (Q)
IDDO (Q)
Typ Max
Unit
0.26 0.35
mA
0.11 0.20
mA
Test Conditions
IDD1 (Q)
IDD2 (Q)
0.6 1.0
mA
DC to 1 MHz logic signal frequency
0.2 0.6
mA
DC to 1 MHz logic signal frequency
IDD1 (10)
2.2 3.4
mA
IDD2 (10)
0.7 1.1
mA
IIA, IIB
−10
+0.01 +10
μA
VIH
0.7 × VDD1
V
VIL
0.3 × VDD1 V
VOAH, VOBH VDD2 − 0.1 3.0
V
VDD2 − 0.5 2.8
V
VOAL, VOBL
0.0 0.1
V
0.04 0.1
V
0.2 0.4
V
5 MHz logic signal frequency
5 MHz logic signal frequency
0 V ≤ VIA, VIB, ≤ VDD1
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
PW
10
tPHL, tPLH
20
PWD
tPSK
tPSKCD
tPSKOD
tR/tF
|CMH|
25
|CML|
25
fr
IDDI (D)
IDDO (D)
100
60
3
5
22
3
22
3.0
35
35
1.1
0.10
0.03
ns
Mbps
ns
ns
ps/°C
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ns
CL = 15 pF, CMOS signal levels
ns
kV/μs
kV/μs
Mbps
mA/Mbps
CL = 15 pF, CMOS signal levels
VIx = VDD1, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
mA/Mbps
1 _{The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load}
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 4 through Figure 6 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for
total VDD1 and VDD2 supply currents as a function of data rate.
2 _{The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.}
3 _{The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.}
4 _{tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is}
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
Rev. C | Page 5 of 20