ADSP-2192M_15 Datasheet, PDF (5/40 Pages) Analog Devices – DSP Microcomputer

ADSP-2192M
PAGE 2
PAGE 1
PAGE 0
DSP P0
MEMORY MAP
ADDRESS
SHARED RAM
(16 ؋ 4K)
0x02 0FFF
0x02 0000
0x01 FFFF
RESE RVED
PROGRAM ROM
24 ؋ 4K
0x01 5000
0x01 4FFF
0x01 4000
PROGRAM RAM
(24 ؋ 16K)
0x01 3FFF
0x01 0000
DATA RAM
BLO CK3
(16 ؋ 16K)
0x00 FFFF
0x00 C000
DATA RAM
BLO CK2
(16 ؋ 16K)
0x00 BFFF
0x00 8000
DATA RAM
BLO CK1
(16 ؋ 16K)
0x00 7FFF
0x00 4000
DATA RAM
BLO CK0
(16 ؋ 16K)
0x00 3FFF
0x00 0000
SAME
PAGE 2
PAGE 1
SHARED
DSP I/O
MAPPED
REGISTERS
ADDRE SS
0xFF FF
PAGE 0
PAGES 0 255
(16 ؋ 256)
0x00 00
DSP P1
MEMORY MAP
ADDRESS
SHARED RAM
(16 ؋ 4K)
0x02 0FF F
0x02 0000
0x01 FFFF
RES ERVED
PROGRAM ROM
24 ؋ 4K
0x01 5000
0x01 4FF F
0x01 4000
PROGRAM RAM
(24 ؋ 16K)
0x01 3FF F
0x01 0000
0x00 FFFF
RES ERVED
DATA RAM
BLO CK1
(16 ؋ 16K)
DATA RAM
BLO CK0
(16 ؋ 16K)
0x00 8000
0x00 7FF F
0x00 4000
0x00 3FF F
0x00 0000
Figure 2. ADSP-2192M Internal/External Memory, Boot Memory, and I/O Memory Maps
Table 2 shows the interrupt vector and DSP-to-DSP semaphores
at reset of each of the peripheral interrupts. The peripheral inter-
rupt’s position in the IMASK and IRPTL register and its vector
address depend on its priority level, as shown in Table 2.
Table 1. DSP-to-DSP Semaphores Register Table
Flag
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Direction
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Function
DSP–DSP Semaphore 0
DSP–DSP Semaphore 1
DSP–DSP Interrupt
Reserved
Reserved
Reserved
Reserved
Register Bus Lock
DSP–DSP Semaphore 0
DSP–DSP Semaphore 1
DSP–DSP Interrupt
Reserved
AC’97 Register–PDC Bus Access
Status
PDC Interface Busy Status (write
from DSP pending)
Reserved
Register Bus Lock Status
Table 2. Vector Table
Bit Priority Interrupt
Vector
Address
Offset¹
01
12
23
34
45
56
67
78
89
9 10
10 11
11 12
12 13
13 14
14 15
15 16
Reset (non-maskable)
Power-Down (non-
maskable)
Kernel interrupt
(single step)
Stack Status
Mailbox
Timer
GPIO
PCI Bus Master
DSP–DSP
FIFO0 Transmit
FIFO0 Receive
FIFO1 Transmit
FIFO1 Receive
Reserved
Reserved
AC’97 Frame
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
1_{The interrupt vector address values are represented as offsets from}
address 0x01 0000. This address corresponds to the start of Program
Memory in DSP P0 and P1.
REV. 0
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