AD9956 Datasheet, PDF (5/32 Pages) Analog Devices – 2.7 GHz DDS-Based AgileRF

Parameter
LOGIC INPUTS (SDI/O, I/O_RESET, RESET,
I/O_UPDATE, PS0 to PS2, SYNC_IN)
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL Input Current
CIN, Maximum Input Capacitance
LOGIC OUTPUTS (SDO, SYNC_OUT, PLL_LOCK)⁶
VOH, Output High Voltage
VOH, Output Low Voltage
IOH
IOL
POWER CONSUMPTION
Total Power Consumed, All Functions On
IAVDD
IDVDD
IDVDD_I/O
ICP_VDD
Power-Down Mode
WAKE-UP TIME (from Power-Down Mode)
Digital Power-Down (CFR1<7>)
DAC Power-Down (CFR2<39>)
RF Divider Power-Down (CFR2<23>)
Clock Driver Power-Down (CFR2<20>)
Charge Pump Full Power-Down (CFR2<4>)
Charge Pump Quick Power-Down (CFR2<3>)
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Output Capacitance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
10 MHz Analog Out
40 MHz Analog Out
80 MHz Analog Out
120 MHz Analog Out
160 MHz Analog Out
Narrowband SFDR
10 MHz Analog Out (±1 MHz)
10 MHz Analog Out (±250 kHz)
10 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
Min
Typ
2.0
±1
3
2.7
100
100
80
12
7
400
6
10
150
14
10
−10
5
AVDD − 0.50
−64
−62
−60
−55
−55
−89
−91
−93
−87
−89
−91
−85
−87
−89
−83
−85
−87
Max
Unit
V
0.8
V
±5
µA
pF
V
0.4
V
µA
µA
400
mW
85
mA
45
mA
20
mA
15
mA
mW
ns
µs
ns
µs
µs
ns
15
+10
0.6
AVDD + 0.50
Bits
mA
% FS
µA
pF
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. 0 | Page 5 of 32
AD9956
Test Conditions/Comments