AD9824_15 Datasheet, PDF (5/24 Pages) Analog Devices – Complete 14-Bit 30 MSPS CCD Signal Processor

AD9824
TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7,
Serial Timing in Figures 21–24.)
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth*
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
t_CP
33
t_ADC
13
t_SHP
5
t_SHD
5
t_CDM
4
t_COB
2
t_S1
0
t_S2
15
t_ID
t_INH
10
t_OD
t_H
7.0
33
16.7
8.3
8.3
10
20
8.3
16.7
3.0
13
16
7.6
9
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
f_SCLK
10
t_LS
10
t_LH
10
t_DS
10
t_DH
10
t_DV
10
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS
Parameter
With
Respect
To
Min Max
Unit
AVDD1, AVDD2
AVSS
DVDD1, DVDD2
DVSS
DRVDD
DRVSS
Digital Outputs
DRVSS
SHP, SHD, DATACLK DVSS
CLPOB, CLPDM, PBLK DVSS
SCK, SL, SDATA
DVSS
VRT, VRB, CMLEVEL AVSS
BYP1-3, CCDIN
AVSS
Junction Temperature
Lead Temperature (10 sec)
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
150
°C
300
°C
ORDERING GUIDE
Model
AD9824KCP
Temperature
Range
–20°C to +85°C
Package
Description
LFCSP
Package
Option
CP-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LFCSP Package
θ_JA = 26°C/W*
*^θJA ^{is measured using a 4-layer PCB with the exposed paddle}
soldered to the board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9824 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–