AD9752ARUZ Datasheet, PDF (5/23 Pages) Analog Devices – 12-Bit, 125 MSPS High Performance TxDAC D/A Converter

PIN CONFIGURATION
(MSB) DB11 1
28 CLOCK
DB10 2
27 DVDD
DB9 3
26 DCOM
DB8 4
25 NC
DB7 5 _{AD9752 24 AVDD}
DB6 6 _{TOP VIEW} 23 ICOMP
DB5 7 ^{(Not to Scale)} _{22 IOUTA}
DB4 8
21 IOUTB
DB3 9
20 ACOM
DB2 10
19 NC
DB1 11
18 FS ADJ
DB0 12
17 REFIO
NC 13
16 REFLO
NC 14
15 SLEEP
NC = NO CONNECT
AD9752
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2–11
12
13, 14,
19, 25
15
16
17
18
19
20
21
22
23
24
26
27
28
Name
Description
DB11
Most Significant Data Bit (MSB).
DB10–DB1 Data Bits 1–10.
DB0
Least Significant Data Bit (LSB).
NC
SLEEP
REFLO
REFIO
FS ADJ
NC
ACOM
IOUTB
IOUTA
ICOMP
AVDD
DCOM
DVDD
CLOCK
No Internal Connection.
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated
if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
No Connect.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
Analog Supply Voltage (+4.5 V to +5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
REV. 0
–5–