AD9219 Datasheet, PDF (5/52 Pages) Analog Devices – Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter

AD9219
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter¹
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage²
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D+, D−), (ANSI-644)¹
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D+, D−),
(Low Power, Reduced Signal Option)¹
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature Min
AD9219-40
Typ Max
AD9219-65
Min Typ Max
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
Full
250
250
Full
1.2
1.2
25°C
20
20
25°C
1.5
1.5
Full
1.2
3.6
Full
0
0.3
25°C
30
25°C
0.5
1.2
3.6
0.3
30
0.5
Full
1.2
3.6
Full
0
0.3
25°C
70
25°C
0.5
1.2
3.6
0.3
70
0.5
Full
1.2
DRVDD + 0.3 1.2
DRVDD + 0.3
Full
0
0.3
0
0.3
25°C
30
30
25°C
2
2
Full
1.79
1.79
Full
0.05
0.05
LVDS
LVDS
Full
247
454
247
454
Full
1.125
1.375
1.125
1.375
Offset binary
Offset binary
LVDS
LVDS
Full
150
250
150
250
Full
1.10
1.30
1.10
1.30
Offset binary
Offset binary
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V
1 _{See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.}
2 _{This is specified for LVDS and LVPECL only.}
Rev. 0 | Page 5 of 52