AD7984 Datasheet, PDF (5/24 Pages) Analog Devices – 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN

AD7984
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.¹
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1 _{See Figure 2 and Figure 3 for load conditions.}
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
300
250
750
10
10.5
12
13
15
11.5
13
14
16
4.5
4.5
3
tEN
tDIS
tSSDICNV
5
tHSDICNV
2
tHSDICNV
0
tSSCKCNV
5
tHSCKCNV
5
tSSDISCK
2
tHSDISCK
3
tDSDOSDI
Typ Max Unit
500 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.5
ns
11
ns
12
ns
14
ns
10
ns
15
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
500µA I_OL
TO SDO
C_L
20pF
500µA I_OH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
X% VIO¹
t_DELAY
V_IH2
V_IL2
Y% VIO¹
t_DELAY
V_IH2
V_IL2
1_{FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.}
2_{MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS}
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
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