AD7944 Datasheet, PDF (5/28 Pages) Analog Devices – 14-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP

AD7944
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.¹
Table 4.
Parameter
Conversion Time: CNV Rising Edge
to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Read During Conversion
Quiet Time During Acquisition from Last SCK
Falling Edge to CNV Rising Edge
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D13 MSB Valid
CNV or SDI High or Last SCK Falling Edge
to SDO High Impedance
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge
SCK Valid Setup Time from CNV Rising Edge
SCK Valid Hold Time from CNV Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
SDI High to SDO High
Symbol
tCONV
tCONV
tACQ
tCYC
tCYC
tCNVH
tDATA
tDATA
tQUIET
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Test Conditions/Comments
Min
Turbo mode
320
Normal mode
420
80
Turbo mode
400
Normal mode
500
CS mode
10
Turbo mode
Normal mode
20
CS mode
9
Chain mode
11
3.5
3.5
2
CS mode
4
CS mode
0
Chain mode
0
Chain mode
5
Chain mode
5
Chain mode
2
Chain mode
3
Chain mode with busy indicator
Typ
Max
190
290
4
5
8
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 _{See Figure 2 and Figure 3 for load conditions.}
500µA I_OL
TO SDO
C_L
20pF
1.4V
500µA I_OH
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
t_DELAY
V_IH1
V_IL1
10% VIO
t_DELAY
V_IH1
V_IL1
1_{MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS}
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 28