AD7938-6_15 Datasheet, PDF (5/32 Pages) Analog Devices – 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer

Data Sheet
AD7938-6
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; fCLKIN = 10MHz, fSAMPLE = 625 kSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 3.
Parameter¹
fCLKIN ²
tQUIET
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13 ³
t14 ⁴
t15
t16
t17
t18
t19
t20
t21
t22
Limit at TMIN, TMAX
700
10
30
10
15
50
0
0
10
10
10
10
0
0
30
30
3
50
0
0
10
0
10
40
15.7
7.8
Unit
kHz min
MHz
max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Description
CLKIN frequency
Minimum time between end of read and start of next conversion, that is, time from when
the data bus goes into three-state until the next falling edge of CONVST.
CONVST pulse width.
CONVST falling edge to CLKIN falling edge setup time.
CLKIN falling edge to BUSY rising edge.
CS to WR setup time.
CS to WR hold time.
WR pulse width.
Data setup time before WR.
Data hold after WR.
New data valid before falling edge of BUSY.
CS to RD setup time.
CS to RD hold time.
RD pulse width.
Data access time after RD.
Bus relinquish time after RD.
Bus relinquish time after RD.
HBEN to RD setup time.
HBEN to RD hold time.
Minimum time between reads/writes.
HBEN to WR setup time.
HBEN to WR hold time.
CLKIN falling edge to BUSY falling edge.
CLKIN low pulse width.
CLKIN high pulse width.
1 _{Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of}
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 35, Figure 36, Figure 37, and Figure 38).
2 _{Minimum CLKIN for specified performance, with slower CLKIN frequencies performance specifications apply typically.}
3 _{The time required for the output to cross 0.4 V or 2.4 V.}
4 _{t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or}
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. C | Page 5 of 32