AD7923_11 Datasheet, PDF (5/24 Pages) Analog Devices – 4-Channel, 200 kSPS 12-Bit ADC with Sequencer in 16-Lead TSSOP

AD7923
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.¹
Table 2.
Parameter
fSCLK ²
tCONVERT
tQUIET
AVDD = 3 V
10
20
16 × tSCLK
50
Limit at TMIN, TMAX
AVDD = 5 V Unit
10
kHz min
20
MHz max
16 × tSCLK
50
ns min
t2
10
10
ns min
t3 ³
35
30
ns max
t43
40
40
ns max
t5
0.4 × tSCLK
0.4 × tSCLK
ns min
t6
0.4 × tSCLK
0.4 × tSCLK
ns min
t7
10
10
ns min
t8 ⁴
15/45
15/35
ns min/max
t9
10
10
ns min
t10
5
5
ns min
t11
20
20
ns min
t12
1
1
μs max
Description
Minimum quiet time required between CS rising edge and start of next
conversion
CS to SCLK set-up time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Sixteenth SCLK falling edge to CS high
Power-Up time from full power-down/auto shutdown mode
1 _{Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.}
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 _{The mark/space ratio for the SCLK input is 40/60 to 60/40.}
3 _{Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.}
4 _{t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated}
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish
time of the part and is independent of the bus loading.
200μA
I_OL
TO OUTPUT
PIN C_L
50pF
200μA
I_OH
1.6V
Figure 2. Load Circuit for Digital Output Timing Specification
Rev. C | Page 5 of 24