AD7804_15 Datasheet, PDF (5/28 Pages) Analog Devices – 3.3 V to 5 V Quad/Octal 10-Bit DACs

AD7804/AD7805/AD7808/AD7809
AD7805/AD7809 TIMING CHARACTERISTICS¹ (VDD= 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V; Reference
= Internal Reference. All specifications T_MIN to T_MAX unless otherwise noted.)
Parameter
Limit at T_MIN, T_MAX
All Versions
Unit
Description
t₁
25
t₂
4.5
t₃
25
t₄
4.5
t₅
25
t₆
4.5
t_6A
6
t₇
40
t₈
0
t₉
40
t₁₀
100
t₁₁
40
t₁₂
100
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Mode Valid to Write Setup Time
Mode Valid to Write Hold Time
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
LDAC Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulsewidth
Time Between Successive Writes
LDAC, CLR Pulsewidth
Write to LDAC Setup Time
NOTE
1_{Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and}
timed from a voltage of (V_IL + V_IH)/2.
Specifications subject to change without notice.
MODE
A0, A1, A2
t₁
t₂
t₄
t₃
CS
WR
DATA
LDAC ¹
LDAC ²
t₈
t₇
t₉
t₆
t₅
t_6A
t₁₂
t₁₀
t₁₁
t₁₁
CLR
1_{TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.}
2_{TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.}
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
REV. A
–5–