AD7792_07 Datasheet, PDF (5/32 Pages) Analog Devices – 3-Channel, Low Noise, Low Power, 16-/24-Bit Σ-Δ ADC with On-Chip In-Amp and Reference

AD7792/AD7793
Parameter
SCLK, CLK, and DIN (Schmitt-
Triggered Input)²
VT(+)
VT(–)
VT(+) − VT(−)
VT(+)
VT(–)
VT(+) − VT(−)
Input Currents
Input Capacitance
LOGIC OUTPUTS (INCLUDING CLK)
VOH, Output High Voltage²
VOL, Output Low Voltage²
VOH, Output High Voltage²
VOL, Output Low Voltage²
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
SYSTEM CALIBRATION²
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS⁷
Power Supply Voltage
AVDD to GND
DVDD to GND
Power Supply Currents
IDD Current
IDD (Power-Down Mode)
AD7792B/AD7793B ¹
1.4/2
0.8/1.7
0.1/0.17
0.9/2
0.4/1.35
0.06/0.13
±10
10
DVDD − 0.6
0.4
4
0.4
±10
10
Offset binary
+1.05 × FS
−1.05 × FS
0.8 × FS
2.1 × FS
2.7/5.25
2.7/5.25
140
185
400
500
1
Unit
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
μA max
pF typ
V min
V max
V min
V max
μA max
pF typ
V max
V min
V min
V max
V min/max
V min/max
μA max
μA max
μA max
μA max
μA max
Test Conditions/Comments
DVDD = 5 V
DVDD = 5 V
DVDD = 5 V
DVDD = 3 V
DVDD = 3 V
DVDD = 3 V
VIN = DVDD or GND
All digital inputs
DVDD = 3 V, ISOURCE = 100 μA
DVDD = 3 V, ISINK = 100 μA
DVDD = 5 V, ISOURCE = 200 μA
DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY)/800 μA
(CLK)
110 μA typ @ AVDD = 3 V, 125 μA typ @ AVDD = 5 V,
unbuffered mode, external reference
130 μA typ @ AVDD = 3 V, 165 μA typ @ AVDD = 5 V,
buffered mode, gain = 1 or 2, external reference
300 μA typ @ AVDD = 3 V, 350 μA typ @ AVDD = 5 V,
gain = 4 to 128, external reference
400 μA typ @ AVDD = 3 V, 450 μA typ @ AVDD = 5 V,
gain = 4 to 128, internal reference
1 _{Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal}
mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AVDD − 16 V typically. When this voltage is exceeded,
the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the
absolute voltage on the analog input pins needs to be below AVDD − 1.6 V.
2 _{Specification is not production tested, but is supported by characterization data at initial product release.}
3 _{Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.}
4 _{Recalibration at any temperature removes these errors.}
5 _{Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C).}
6 _{FS[3:0] are the four bits used in the mode register to select the output word rate.}
7 _{Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled.}
Rev. B | Page 5 of 32