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| AD7766 Datasheet, PDF (5/18 Pages) Analog Devices – 24-Bit, 10mW, 125ksps Analog to Digital Converter in 16 lead TSSOP | |||
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Preliminary Technical Data
TIMIMG DIAGRAMS
AD7766
MCLK
DRDY
t2
1
8*n
1
t3
t4
t1
t5
tREAD
8*n
t5
tDRDY
Figure 2.DRDY versus MCLK TimingDiagram. For AD7766 n=1(Decimate by8), AD7766-1 n=2(Decimate by 16), AD7766-2 n = 4(Decimate by 32).
DRDY
CS
SCLK
SDO
CS = 0
DRDY
SCLK
SDO
tDRDY
tREAD
t13
t6
t10
1
t8
t7
t11
t9
MSB
D22
D21
D20
23
t12
D1
LSB
Figure 3.Serial timing diagram, reading data using CS
DATA
INVALID
tDRDY
tREAD
t14
1
MSB
t8
D22
t10
t11
t9
D21
D20
23
D1
Figure 4.Serial timing diagram, reading data setting CS logic low.
24
LSB
t15
DATA
INVALID
Rev. PrD | Page 5 of 18
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