AD561JNZ Datasheet, PDF (5/8 Pages) Analog Devices – Low Cost 10-Bit Low Cost 10-Bit

AD561
UNIPOLAR CONFIGURATION
This configuration, shown in Figure 2, will provide a unipolar
0 V to +10 V output range.
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust op amp trimmer, R₁, until the
output reads 0.000 volts (1 LSB = 9.76 mV).
STEP 11. . . GAIN ADJUST
Turn all bits ON and adjust 50 Ω gain trimmer, R₂, until the
output is 9.990 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.23 V full scale is desired
(exactly 10 mV/bit), insert a 120 Ω resistor in series with R₂.
BIPOLAR CONFIGURATION
This configuration, shown in Figure 3, will provide a bipolar
output voltage from –5.000 to +4.990 volts, with positive full
scale occurring with all bits ON (all 1s).
STEP 1. . . ZERO ADJUST
Turn ON MSB only, turn OFF all other bits. Adjust 50 Ω
trimmer R₃, to give 0.000 output volts. For maximum resolution
a 120 Ω resistor may be placed in parallel with R₃.
STEP 11. . . GAIN ADJUST
Turn OFF all bits, adjust 50 Ω gain trimmer to give a reading of
–5.000 volts.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
the op amp trimmer is unnecessary unless the untrimmed offset
drift of the op amp is excessive.
؎10 VOLT BUFFERED BIPOLAR OUTPUT
The AD561 can also be connected for a ± 10 volt bipolar range
with an additional external resistor as shown in Figure 4. A
larger value trimmer is required to compensate for tolerance in
the thin film resistors, which are trimmed to match the full-scale
current. For best full scale temperature coefficient performance,
the external resistors should have a TC of –50 ppm/°C.
CIRCUIT DESCRIPTION
A simplified schematic with the essential circuit features of the
AD561 is shown in Figure 5. The voltage reference, CR1, is a
buried Zener (or subsurface breakdown diode). This device
exhibits far better all-around performance than the NPN base-
emitter reverse-breakdown diode (surface Zener), which is in
nearly universal use in integrated circuits as a voltage reference.
Greatly improved long-term stability and lower noise are the
major benefits the buried Zener derives from isolating the
breakdown point from surface stress and mobile oxide charge
effects. The nominal 7.5 volt device (including temperature
compensation circuitry) is driven by a current source to the
negative supply so the positive supply can be allowed to drop as
low as 4.5 volts. The temperature coefficient of each diode is
individually determined; this data is then used to laser trim a
compensating circuit to balance the overall TC to zero. The
typical resulting TC is 0 to ± 15 ppm/°C. The negative reference
level is inverted and scaled by A₁ to give a +2.5 volt reference,
which can be driven by the low positive supply. The AD561,
packaged in the 16-pin DIP, has the +2.5 volt reference (REF
OUT) connected directly to the input of the control amplifier
(REF IN). The buffered reference is not directly available
externally except through the 2.5 kΩ bipolar offset resistor.
Figure 2. 0 V to +10 V Unipolar Voltage Output
Figure 3. ±5 V Buffered Bipolar Voltage Output
Figure 4. ±10 V Buffered Voltage Output
The 2.5 kΩ scaling resistor and control amplifier A₂ then force a
1 mA reference current to flow through reference transistor Q₁,
which has a relative emitter area of 8A. This is accomplished by
forcing the bottom of the ladder to the proper voltage. Since Q₁
and Q₂ have equal emitter areas and equal 5 kΩ emitter resistors,
Q₂ also carries 1 mA. The ladder voltage drop constrains Q₇
(with area 4A) to carry only 0.5 mA; Q₈ carries 0.25 mA, etc.
The first four significant bit cells are exactly scaled in emitter
area to match Q₁ for optimum V_BE and V_BE drift match, as well
as for beta match. These effects are insignificant for the lower
order bits, which account for a total of only 1/16 of full scale.
However, the 18 mV V_BE difference between two matched
transistors carrying emitter currents in a ratio of 2:1 must be
corrected. This is achieved by forcing 120 µA through the
150 Ω interbase resistors. These resistors, and the R-2R ladder
resistors, are actively laser-trimmed at the wafer level to bring
total device accuracy to better than 1/4 LSB. Sufficient ratio
accuracy in the last two bits is obtained by simple emitter area
REV. A
–5–