AD5429_15 Datasheet, PDF (5/29 Pages) Analog Devices – Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface

AD5429/AD5439/AD5449
Parameter¹
Min
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough
Typ Max Unit
70
dB
48
dB
12
17
pF
25
30
pF
3
5
nV-sec
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
2.5
IDD
Power Supply Sensitivity
25
81
61
66
55
63
65
50
60
62
73
80
87
70
75
80
72
65
5.5
0.7
0.5
10
0.001
1 _{Guaranteed by design and characterization, not subject to production test.}
nV/√Hz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
µA
µA
%/%
Data Sheet
Conditions
DAC latches loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
VREF = 3. 5 V p-p, all 1s loaded, f = 1 kHz
Clock = 10 MHz, VREF = 3.5 V
AD5449, 65k codes, VREF = 3.5 V
AD5449, 65k codes, VREF = 3.5 V
AD5449, 65k codes, VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
Rev. E | Page 4 of 28