AD5372_15 Datasheet, PDF (5/29 Pages) Analog Devices – 32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC

AD5372/AD5373
SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V;
CL = open circuit; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Full-Scale Error
Gain Error
Zero-Scale Error²
Full-Scale Error²
Span Error of Offset DAC
VOUTx Temperature Coefficient
DC Crosstalk²
REFERENCE INPUTS (VREF0, VREF1)²
VREFx Input Current
VREFx Range
SIGGND INPUTS (SIGGND0 TO SIGGND3)²
DC Input Impedance
Input Range
SIGGNDx Gain
OUTPUT CHARACTERISTICS²
Output Voltage Range
Nominal Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
CLR High Impedance Leakage Current
Input Capacitance²
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage
Output High Voltage (SDO)
SDO High Impedance Leakage Current
High Impedance Output Capacitance²
AD5372¹
B Version
16
±4
±1
±10
±10
0.1
1
1
±35
5
100
±10
2/5
50
±0.5
0.995/1.005
VSS + 1.4
VDD − 1.4
−4 to +8
15
±1
2200
0.5
1.7
2.0
0.8
±1
±20
10
0.5
DVCC − 0.5
±5
10
AD5373¹
B Version
14
±1
±1
±10
±10
0.1
1
1
±35
5
100
±10
2/5
50
±0.5
0.995/1.005
VSS + 1.4
VDD − 1.4
−4 to +8
15
±1
2200
0.5
1.7
2.0
0.8
±1
±20
10
0.5
DVCC − 0.5
±5
10
Unit
Bits
LSB max
LSB max
mV max
mV max
% FSR
LSB typ
LSB typ
mV max
ppm FSR/°C typ
μV max
μA max
V min/V max
kΩ min
V min/V max
min/max
V min
V max
V min/V max
mA max
mA max
pF max
Ω max
V min
V min
V max
μA max
μA max
pF max
V max
V min
μA max
pF typ
Test Conditions/Comments²
Guaranteed monotonic by design over
temperature
Before calibration
Before calibration
Before calibration
After calibration
After calibration
See the Offset DACS section for details
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale,
full-scale change on any other channel
Per input; typically ±30 nA
±2% for specified operation
Typically 55 kΩ
ILOAD = 1 mA
ILOAD = 1 mA
VOUTx to DVCC, VDD, or VSS
JEDEC compliant
DVCC = 2.5 V to 3.6 V
DVCC = 3.6 V to 5.5 V
DVCC = 2.5 V to 5.5 V
Excluding CLR pin
Sinking 200 μA
Sourcing 200 μA
Rev. C | Page 4 of 28