AD5258BRMZ1-RL7 Datasheet, PDF (5/24 Pages) Analog Devices – Nonvolatile, I2C-Compatible 64-Position, Digital Potentiometer

Data Sheet
AD5258
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
I²C INTERFACE TIMING CHARACTERISTICS
SCL Clock Frequency
tBUF Bus-Free Time Between Stop and Start
tHD;STA Hold Time (Repeated start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for Stop Condition
EEPROM Data Storing Time
EEPROM Data Restoring Time at Power On¹
EEPROM Data Restoring Time upon Restore
Command¹
EEPROM Data Rewritable Time²
FLASH/EE MEMORY RELIABILITY
Endurance³
Data Retention⁴
Symbol
Conditions
fSCL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
tEEMEM_STORE
tEEMEM_RESTORE1
tEEMEM_RESTORE2
After this period, the first clock pulse is
generated.
VDD rise time dependant. Measure with-
out decoupling capacitors at VDD and GND.
VDD = 5 V.
tEEMEM_REWRITE
Min Typ Max Unit
0
400 kHz
1.3
µs
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
0.9 µs
100
ns
300 ns
300 ns
0.6
µs
26
ms
300
µs
300
µs
540
µs
100 700
100
kCycles
Years
1 _{During power-up, the output is momentarily preset to midscale before restoring EEPROM content.}
2 _{Delay time after power-on preset prior to writing new EEPROM data.}
3 _{Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and is measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.}
4 _{Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates}
with junction temperature.
SCL
t₈
t₉
t₆
t₂
t₃
t₄
t₅
t₇
t₈ ^t9
SDA
t₁
P
S
Figure 3. I²C Interface Timing Diagram
t₁₀
P
Rev. D | Page 5 of 24