AD5060BRJZ-1500RL7 Datasheet, PDF (5/24 Pages) Analog Devices – Fully Accurate 14-/16-Bit VOUT nanoDAC™ SPI Interface 2.7 V to 5.5 V, in an SOT-23

TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX_, unless otherwise noted.
Table 3.
Parameter
t1 ²
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
Limit¹
33
5
3
10
3
2
0
12
9
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
1 _{All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.}
2 _{Maximum SCLK frequency is 30 MHz.}
SCLK
SYNC
DIN
t₄
t₈
D23
t₂
t₁
t₃
t₆
t₅
D22
D2
D1
t₉
t₇
D0
Figure 2. AD5060 Timing Diagram
AD5040/AD5060
D23
D22
Rev. A | Page 5 of 24