AD1862_15 Datasheet, PDF (5/12 Pages) Analog Devices – Ultralow Noise 20-Bit Audio DAC

AD1862
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the value of the fundamental
input frequency. It is usually expressed in percent (%) or deci-
bels (dB).
D-RANGE DISTORTION
D-Range Distortion is the ratio of the signal amplitude to the
distortion plus noise at –60 dB. In this case, an A-Weight filter
is used. The value specified for D-Range performance is the ra-
tio measured plus 60 dB.
NR1
V_S
V_REF
AGND
NR2
LATCH
ENABLE
– V_L
CLOCK
TRIM
ADJ
20-BIT DAC
LATCH
DECODER AND
DIGITAL OFFSET
FEEDBACK
REGISTER
CURRENT
OUTPUT
+ V_L
OBSOLETE SETTLING TIME
Settling Time is the time required for the output to reach and
remain within ± 1/2 LSB about its final value, measured from
the digital input transition. It is a primary measure of dynamic
performance and is usually expressed in nanoseconds (ns).
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise Ratio is defined as the ratio of the ampli-
tude of the output with full-scale present to the amplitude of the
output when no signal is present. It is expressed in decibels (dB)
and measured using an A-Weight filter.
GAIN LINEARITY
Gain Linearity is a measure of the deviation of the actual output
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a low level. A perfect
D/A converter exhibits no difference between the ideal and ac-
DATA
DGND
SERIAL INPUT
REGISTER
AD1862 Block Diagram
FUNCTIONAL DESCRIPTION
The AD1862 is a high performance, monolithic 20-bit audio
DAC. Each device includes a voltage reference, a 20-bit DAC,
20-bit input latch and a 20-bit serial-to-parallel input register. A
special digital offset circuit, combined with segmentation cir-
cuitry, produces excellent THD+N and D-range performance.
Extensive noise-reduction features are utilized to make the noise
performance of the AD1862 as high as possible. For example,
the voltage reference circuit is a low-noise, 9 volt bandgap cell.
This cell supplies the reference voltage to the bipolar offset cir-
cuit and the DAC. An external noise-reduction capacitor is con-
nected to NR1 to form a low-pass filter network.
tual amplitudes. Gain linearity is expressed in decibels (dB).
Additional noise-reduction techniques are used in the control
amplifier of the DAC. By connecting an external noise-reduction
MIDSCALE ERROR
Midscale Error, or bipolar zero error, is the deviation of the ac-
capacitor to NR2 output noise contributions from the control
portion of the DAC are similarly reduced. The noise-reduction
tual analog output from the ideal output when the 2s comple-
efforts result in a signal-to-noise ratio of 120 dB.
ment input code representing midscale is loaded in the input
register. The AD1862 is a current output D/A converter. There-
fore, this error is expressed in µA.
The design of the AD1862 uses a combination of segmented de-
coder, R-2R topology and digital offset to produce low distor-
tion at all signal amplitudes. The digital offset technique shifts
the midscale output voltage (0 V) away from the MSB transition
of the device. Therefore, small amplitude signals are not af-
fected by an MSB change. An extra DAC cell is included to
avoid clipping the output at full scale.
The DAC supplies a ± 1 mA output current to an external
I-to-V converter. An on-board 3 kΩ feedback resistor is also
supplied. Both the output current and feedback resistor are
laser-trimmed to ± 2% tolerance, simplifying the selection of
external filter and/or deemphasis network components. The in-
put register and serial-to-parallel converter are fabricated with
CMOS logic gates. These gates allow the achievement of fast
switching speeds and low power consumption. Internal TTL-
to-CMOS converters are used to insure TTL and 5 V CMOS
compatibility.
REV. A
–5–