AD7172-4 Datasheet, PDF(49/61 Page) Analog Devices – Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers

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AD7172-4 Datasheet, PDF (49/61 Pages) Analog Devices – Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers

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Data Sheet

AD7172-4

ADC MODE REGISTER

Address: 0x01, Reset: 0x2000, Name: ADCMODE

The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets

the filter and the RDY bits and starts a new conversion or calibration.

Table 28. Bit Descriptions for ADCMODE

Bits Bit Name

Settings Description

RESERVED

Reserved

HIDE_DELAY

If a programmable delay is set using the DELAY bits, this bit allows the

delay to be hidden by absorbing the delay into the conversion time for

selected data rates with the sinc5 + sinc1 filter. See the Delay section for

more information.

0 Enabled

1 Disabled

SING_CYC

This bit can be used when only a single channel is active to set the ADC

to only output at the settled filter data rate.

0 Disabled

1 Enabled

[12:11] RESERVED

These bits are reserved; set these bits to 0.

[10:8] DELAY

These bits allow a programmable delay to be added after a channel

switch to allow settling of external circuitry before the ADC starts

processing its input.

000 0 Âµs

001 32 Âµs

010 128 Âµs

011 320 Âµs

100 800 Âµs

101 1.6 ms

110 4 ms

111 8 ms

RESERVED

This bit is reserved; set this bit to 0.

[6:4] MODE

These bits control the operating mode of the ADC. See the Operating

Modes section for more information.

000 Continuous conversion mode

001 Single conversion mode

010 Standby mode

011 Power-down mode

100 Internal offset calibration

110 System offset calibration

111 System gain calibration

[3:2] CLOCKSEL

This bit is used to select the ADC clock source. Selecting internal

oscillator also enables the internal oscillator.

00 Internal oscillator

01 Internal oscillator output on the XTAL2/CLKIO pin

10 External clock input on the XTAL2/CLKIO pin

11 External crystal on the XTAL1 and XTAL2/CLKIO pins

[1:0] RESERVED

These bits are reserved; set these bits to 0.

Reset

0x0

0x1

0x0

Access

Rev. A | Page 49 of 61

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