ADUC7129_15 Datasheet, PDF (47/92 Pages) Analog Devices – Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC

ADuC7128/ADuC7129
DDSFRQ Register
Name
Address
DDSFRQ
0xFFFF0694
Default Value
0x00000000
Access
R/W
Table 54. DDSFRQ MMR Bit Designations
Bit
Description
31:0
Frequency select word (FSW)
The DDS frequency is controlled via the DDSFRQ MMR. This
MMR contains a 32-bit word (FSW) that controls the frequency
according to the following formula:
FSW × 20.8896 MHz
Frequency =
2³²
DDSPHS Register
Name
Address
DDSPHS
0xFFFF0698
Default Value
0x00000000
Access
R/W
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brown-out
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
The PSM does not operate correctly when using JTAG debug.
It should be disabled in JTAG debug mode.
COMPARATOR
The ADuC7128/ADuC7129 integrate an uncommitted voltage
comparator. The positive input is multiplexed with ADC2, and
the negative input has two options: ADC3 or the internal refer-
ence. The output of the comparator can be configured to generate
a system interrupt, can be routed directly to the programmable
logic array, can start an ADC conversion, or can be on an
external pin, CMPOUT.
Table 55. DDSPHS MMR Bit Designations
Bit
Description
31:12
Reserved
11:0
Phase
The DDS phase offset is controlled via the DDSPHS MMR. This
MMR contains a 12-bit value that controls the phase of the DDS
output according to the following formula:
Phase
Offset
=
2
×
π× Phase
2¹²
POWER SUPPLY MONITOR
The power supply monitor on the ADuC7128/ADuC7129
indicates when the IOVDD supply pin drops below one of two
supply trip points. The monitor function is controlled via the
PSMCON register (see Table 56). If enabled in the IRQEN or
FIQEN register, the monitor interrupts the core using the PSMI
bit in the PSMCON MMR. This bit is cleared immediately once
CMP goes high. Note that if the interrupt generated is exited
before CMP goes high (IOVDD is above the trip point), no further
interrupts are generated until CMP returns high. The user should
ensure that code execution remains within the ISR until CMP
returns high.
ADC2/CMP0
ADC3/CMP1
P0.0/CMP_OUT
REF
MUX
MUX
PLA
IRQ
ADC START
CONVERSION
Figure 46. Comparator
Hysteresis
Figure 47 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (VOS) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(VH) is ½ the width of the hysteresis range.
COMP_OUT
V_H
V_H
V_OS
COMP0
Figure 47. Comparator Hysteresis Transfer Function
Table 56. PSMCON MMR Bit Designations
Bit
Name
Description
3
CMP
Comparator Bit. This is a read-only bit that directly reflects the state of the comparator.
Read 1 indicates the IOVDD supply is above its selected trip point or the PSM is in power-down mode.
Read 0 indicates the IOVDD supply is below its selected trip point. This bit should be set before leaving
the interrupt service routine.
2
TP
Trip Point Selection Bit.
0 = 2.79 V
1 = 3.07 V
1
PSMEN
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
0
PSMI
Power Supply Monitor Interrupt Bit. This bit is set high by the MicroConverter if CMP is low, indicating low
I/O supply. The PSMI bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit can
be cleared by writing a 1 to this location. A write of 0 has no effect. There is no timeout delay. PSMI can be
cleared immediately once CMP goes high.
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