ADSP-BF525_15 Datasheet, PDF (47/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
SDRAM Interface Timing
Table 37. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
V_DDMEM
1.8V Nominal
V_DDMEM
2.5 V or 3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_SSDAT
Data Setup Before CLKOUT
t_HSDAT
Data Hold After CLKOUT
Switching Characteristics
1.5
1.5
ns
1.3
0.8
ns
t_SCLK
t_SCLKH
t_SCLKL
t_DCAD
t_HCAD
t_DSDAT
t_ENSDAT
CLKOUT Period¹
CLKOUT Width High
CLKOUT Width Low
Command, Address, Data Delay After CLKOUT²
Command, Address, Data Hold After CLKOUT²
Data Disable After CLKOUT
Data Enable After CLKOUT
12.5
10
ns
5.0
4.0
ns
5.0
4.0
ns
5.0
4.0
ns
1.0
1.0
ns
5.5
5.0
ns
0.0
0.0
ns
1 _{The tSCLK value is the inverse of the fSCLK specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.}
2 _{Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.}
Table 38. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
V_DDMEM
1.8V Nominal
V_DDMEM
2.5 V or 3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_SSDAT
Data Setup Before CLKOUT
t_HSDAT
Data Hold After CLKOUT
Switching Characteristics
1.5
1.5
ns
1.0
0.8
ns
t_SCLK
t_SCLKH
t_SCLKL
t_DCAD
t_HCAD
t_DSDAT
t_ENSDAT
CLKOUT Period¹
10
7.5
ns
CLKOUT Width High
2.5
2.5
ns
CLKOUT Width Low
2.5
2.5
ns
Command, Address, Data Delay After CLKOUT²
4.0
4.0
ns
Command, Address, Data Hold After CLKOUT²
1.0
1.0
ns
Data Disable After CLKOUT
5.0
4.0
ns
Data Enable After CLKOUT
0.0
0.0
ns
1 _{The tSCLK value is the inverse of the fSCLK specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.}
2 _{Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.}
Rev. D | Page 47 of 88 | July 2013