AD9691_17 Datasheet, PDF (47/73 Pages) Analog Devices – Dual Analog-to-Digital Converter

AD9691
Data Sheet
User Data and Error Detection
After the initial lane alignment sequence is complete, the user data
is sent. Normally, all characters within a frame are considered
user data. However, to monitor the frame clock and multiframe
clock synchronization, there is a mechanism for replacing
characters with /F/ or /A/ alignment characters when the data
meets certain conditions. These conditions are different for
unscrambled and scrambled data. The scrambling operation
is enabled by default, but it can be disabled using the SPI.
For scrambled data, any 0xFC character at the end of a frame is
replaced by an /F/ character, and any 0x7C character at the end
of a multiframe is replaced with an /A/ character. The JESD204B
receiver (Rx) checks for /F/ and /A/ characters in the received
data stream and verifies that they only occur in the expected
locations. If an unexpected /F/ or /A/ character is found, the
receiver handles the situation by using dynamic realignment or
asserting the SYNCINB± signal for more than four frames to
initiate a resynchronization. For unscrambled data, when the
final character of two subsequent frames is equal, the second
character is replaced with an /F/ character if it is at the end of a
frame, and an /A/ character if it is at the end of a multiframe.
Insertion of alignment characters can be modified using the
SPI. The frame alignment character insertion (FACI) is enabled
by default. For more information on the link controls, see the
Memory Map section, Register 0x571.
8B/10B Encoder
The 8B/10B encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed.
The control characters used in JESD204B are shown in Table 24.
The 8B/10B encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple symbols.
The 8B/10B interface has options that can be controlled via the
SPI. These operations include bypass and invert. These options
are intended to be troubleshooting tools for the verification of
the digital front end (DFE). See the Memory Map section,
Register 0x572, Bits[2:1] for information on configuring the
8B/10B encoder.
Table 24. AD9691 Control Characters Used in JESD204B
Abbreviation Control Symbol 8-Bit Value 10-Bit Value, RD¹ = −1
/R/
/K28.0/
000 11100 001111 0100
/A/
/K28.3/
011 11100 001111 0011
/Q/
/K28.4/
100 11100 001111 0010
/K/
/K28.5/
101 11100 001111 1010
/F/
/K28.7/
111 11100 001111 1000
10-Bit Value, RD¹ = +1
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Description
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
1 _{RD means running disparity.}
Rev. 0 | Page 46 of 72