AD9524 Datasheet, PDF (46/56 Pages) Analog Devices – Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

AD9524
Data Sheet
Table 43. PLL1 Miscellaneous Control
Address Bits Bit Name
0x01C 7 Enable REFB R divider
independent division control
6 OSC_CTRL control voltage to
VCC/2 when reference clock fails
5 Reserved
[4:2] Reference selection mode
[1:0] Reserved
1 _{X = don’t care.}
Description
1: REFB R divider is controlled by Register 0x012 and Register 0x013.
0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010
and Register 0x011). This requires that, for the loop to stay locked, the REFA and
REFB input frequencies must be the same.
High permits the OSC_CTRL control voltage to be forced to midsupply when the
feedback or input clocks fail. Low tristates the charge pump output.
1: OSC_CTRL control voltage goes to VCC/2.
0: OSC_CTRL control voltage tracks the tristated (high impedance) charge pump
(through the buffer).
Reserved.
Programs the REFA, REFB mode selection (default = 000).
REF_SEL
Pin
Bit 4
Bit 3 Bit 2 Description
X¹
0
0
0
Nonrevertive: stay on REFB.
X¹
0
0
1
Revert to REFA.
X¹
0
1
0
Select REFA.
X¹
0
1
1
Select REFB.
0
1
X¹
X¹
REF_SEL pin = 0 (low): REFA.
1
1
X¹
X¹
REF_SEL pin = 1 (high): REFB.
0: reserved (default).
Table 44. PLL1 Loop Filter Zero Resistor Control
Address Bits Bit Name
0x01D [7:4] Reserved
[3:0] PLL1 loop filter, RZERO
Description
Reserved.
Programs the value of the zero resistor, RZERO.
Bit 3
Bit 2 Bit 1 Bit 0 RZERO Value (kΩ)
0
0
0
0
883
0
0
0
1
677
0
0
1
0
341
0
0
1
1
135
0
1
0
0
10
0
1
0
1
10
0
1
1
0
10
0
1
1
1
10
1
0
0
0
Use external resistor
Rev. D | Page 46 of 56