AD9523-1BCPZ Datasheet, PDF (46/60 Pages) Analog Devices – Low Jitter Clock Generator

AD9523-1
Input PLL (PLL1) (Address 0x010 to Address 0x01D)
Table 34. PLL1 REFA R Divider Control
Address Bits Bit Name
0x010 [7:0] REFA R divider
0x011 [1:0]
Description
10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
10-bit REFA R divider, Bits[9:8] (MSB).
Table 35. PLL1 REFB R Divider Control¹
Address Bits Bit Name
0x012 [7:0] REFB R divider
0x013 [1:0]
Description
10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
10-bit REFB R divider, Bits[9:8] (MSB).
1 _{Requires Register 0x01C, Bit 7 = 1 for division that is independent of REFA division.}
Table 36. PLL1 Reference Test Divider
Address Bits Bit Name
0x014 [7:6] Reserved
[5:0] REF_TEST divider
Description
Reserved.
6-bit reference test divider. Divide-by-1 to divide-by-63.
000000, 000001: divide-by-1.
Table 37. PLL1 Reserved
Address Bits Bit Name
0x015 [7:0] Reserved
Description
Reserved.
Table 38. PLL1 Feedback N Divider Control
Address Bits Bit Name
0x016
[7:0] PLL1 feedback N divider control
(N_PLL1)
0x017 [1:0]
Description
10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
10-bit feedback divider, Bits[1:0] (MSB).
Table 39. PLL1 Charge Pump Control
Address Bits Bit Name
0x018 7
PLL1 charge pump tristate
[6:0] PLL1 charge pump control
0x019
[7:5] Reserved
4
Enable SPI control of antibacklash
pulse width
[3:2] Antibacklash pulse width control
[1:0] PLL1 charge pump mode
Description
Tristates the PLL1 charge pump.
These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA
with a full-scale magnitude of ~63.5 μA.
Reserved.
Controls the functionality of Register 0x019, Bits[3:2].
0 (default): the device automatically controls the antibacklash period.
1: antibacklash period defined by Register 0x019, Bits[3:2].
Controls the PFD antibacklash period.
00 (default): minimum.
01: low.
10: high.
11: maximum.
These bits are ineffective unless Register 0x019, Bit 4 = 1.
Controls the mode of the PLL1 charge pump.
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
Rev. B | Page 46 of 60