ADSP-BF539F_15 Datasheet, PDF (45/60 Pages) Analog Devices – Blackfin Embedded Processor

Serial Peripheral Interface Ports—Master Timing
Table 34 and Figure 28 describe SPI ports master operations.
Table 34. Serial Peripheral Interface (SPI) Ports—Master Timing
Parameter
Timing Requirements
t_SSPIDM
Data Input Valid to SCKx Edge (Data Input Setup)
t_HSPIDM
SCKx Sampling Edge to Data Input Invalid
Switching Characteristics
t_SDSCIM
t_SPICHM
t_SPICLM
t_SPICLK
t_HDSM
t_SPITDM
t_DDSPIDM
t_HDSPIDM
SPIxSELy Low to First SCKx edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCKx Edge to SPIxSELy High
Sequential Transfer Delay
SCKx Edge to Data Out Valid (Data Out Delay)
SCKx Edge to Data Out Invalid (Data Out Hold)
ADSP-BF539/ADSP-BF539F
Min
Max
9.0
–1.5
2t_SCLK –1.5
2t_SCLK – 1.5
2t_SCLK – 1.5
4t_SCLK –1.5
2t_SCLK –1.5
2t_SCLK –1.5
5
–1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
t_SDSCIM
t_SPICLM
t_SPICHM
t_SPICLK
t_HDSM
t_SPITDM
SPIxMOSI
(OUTPUT)
CPHA = 1
SPIxMISO
(INPUT)
t_HDSPIDM
t_DDSPIDM
t_SSPIDM
t_HSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
t_SSPIDM
SPIxMISO
(INPUT)
t_HSPIDM
t_HDSPIDM
t_DDSPIDM
Figure 28. Serial Peripheral Interface (SPI) Ports—Master Timing
Rev. F | Page 45 of 60 | October 2013