ADSP-21060KS-160 Datasheet, PDF (44/64 Pages) Analog Devices – SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
RCLK
DATA RECEIVE— INTERNAL CLOCK
DRIVE
EDGE
t_SCLKIW
SAMPLE
EDGE
t_HOFSE
RFS
t_DFSE
t_SFSI
t_SDRI
t_HFSI
t_HDRI
DATA RECEIVE— EXTERNAL CLOCK
DRIVE
EDGE
t_SCLKW
SAMPLE
EDGE
RCLK
t_HOFSE
t_DFSE
t_SFSE
t_HFSE
RFS
t_SDRE
t_HDRE
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT— INTERNAL CLOCK
DRIVE
EDGE
t_SCLKIW
SAMPLE
EDGE
TCLK
t_HOFSI
TFS
t_HDTI
t_DFSI
t_DDTI
t_SFSI
DT
t_HFSI
DATA TRANSMIT— EXTERNAL CLOCK
DRIVE
EDGE
t_SCLKW
SAMPLE
EDGE
TCLK
t_HOFSE
t_DFSE
t_SFSE
t_HFSE
TFS
t_HDTE
t_DDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
TCLK
(EXT)
DT
TCLK
(INT)
t_DDTEN
DRIVE
EDGE
t_DDTIN
TCLK/RCLK
t_{DD TT E}
TCLK/RCLK
DRIVE
EDGE
t_DDTTI
DT
CLKIN
TCLK, RCLK
TFS, RFS, DT
t_DPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
CLKIN
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
TFS (EXT)
t_HTFSCK
t_STFSCK
TCLK (INT)
RCLK (INT)
t_DCLK
LOW TO HIGH ONLY
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
Figure 25. Serial Ports
Rev. F | Page 44 of 64 | March 2008